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EL8188
Data Sheet February 22, 2007 FN7467.3
PRELIMINARY
Micropower Single Supply Rail-to-Rail Input-Output Precision Op Amp
The EL8188 is a micropower precision op amp optimized for single supply operation at 5V and can operate down to 2.4V. The EL8188 draws minimal supply current while meeting excellent DC-accuracy, noise, and output drive specifications. Competing devices seriously degrade these parameters to achieve rail-to-rail operation and microamp supply current. Offset current, voltage and current noise, slew rate, and gain-bandwidth product are all 2X to 10X better than on previous micropower rail-to-rail op amps. The EL8188 can be operated from one lithium cell or two Ni-Cd batteries. The input range includes both the positive and negative rails. The output swings to both rails.
Features
* 50A supply current * 1mV typ offset voltage * 2pA input bias current * 266kHz gain-bandwidth product * 0.13V/s slew rate * Single supply operation down to 2.4V * Rail-to-rail input and output * Output sources and sinks 26mA load current * Pb-free plus anneal available (RoHS compliant)
Applications
* Battery- or solar-powered systems * 4mA to 20mA current loops * Handheld consumer products * Medical devices * Thermocouple amplifiers
Ordering Information
PART NUMBER Coming Soon EL8188FWZ-T7 (Note) PART MARKING 8178FW TAPE & REEL PACKAGE (Pb-Free) PKG. DWG. #
7" 6 Ld SOT-23 MDP0038 (3k pcs) 7" 6 Ld SOT-23 MDP0038 (250 pcs) 97/Tube 8 Ld SO 7" 8 Ld SO (1k pcs) MDP0027 MDP0027
8178FW Coming Soon EL8188FWZ-T7A (Note) EL8188FSZ (Note) EL8188FSZ-T7 (Note) 8178FSZ 8178FSZ
* Photodiode pre-amps * pH probe amplifiers
Pinouts
EL8188 (6 LD SOT-23 - Coming Soon) TOP VIEW
OUT 1 VS- 2 IN+ 3 6 VS+ 5 ENABLE 4 IN-
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
+-
EL8188 (8 LD SO) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 + 8 ENABLE 7 VS+ 6 OUT 5 NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL8188
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (VS) and Pwr-up Ramp Rate . . . . . . . . 5.5V, 1V/s Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Current into IN+, IN-, and ENABLE . . . . . . . . . . . . . . . . . . . . . . 5mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V ESD tolerance, Human Body Model . . . . . . . . . . . . . . . . . . . TBDkV ESD tolerance, Machine Model . . . . . . . . . . . . . . . . . . . . . . . TBDV
Thermal Information
Thermal Resistance JA (C/W) 6 Ld SOT Package . . . . . . . . . . . . . . . . . . . . . . . . . 230 8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Ambient Operating Temperature Range . . . . . . . . -40C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . -65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER VOS V OS -----------------Time V OS --------------T IB
VS+ = 5V, VS- = 0V, VCM = 0.1V, VO = 1.4V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C TEST CONDITIONS SOT MIN TYP 1 1.2 1.1 -15 -600 2 2.1 15 600 2.8 48 0.15 0 80 75 100 5 MAX 4 UNIT mV V/Mo V/C pA pA VP-P nV/Hz pA/Hz V dB dB 100 dB dB 400 V/mV V/mV 15 3 8 10 130 200 300 4.994 4.992 4.750 4.7 0.05 fO = 100kHz 0.13 266 0.25 4.867 4.997 V/mV mV mV mV mV V V V V V/s kHz
DESCRIPTION Input Offset Voltage Long Term Input Offset Voltage Stability Input Offset Drift vs Temperature Input Bias Current
eN
Input Noise Voltage Peak-to-Peak Input Noise Voltage Density
f = 0.1Hz to 10Hz fO = 1kHz fO = 1kHz Guaranteed by CMRR test VCM = 0V to 5V
iN CMIR CMRR
Input Noise Current Density Input Voltage Range Common-Mode Rejection Ratio
PSRR
Power Supply Rejection Ratio
VS = 2.4V to 5V
80 80
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4.5V, RL = 100k to (VS+ + VS-)/2 VO = 0.5V to 4.5V, RL = 1k to (VS+ + VS-)/2
100 100
VOUT
Maximum Output Voltage Swing
VOL; Output low, RL = 100k to (VS+ + VS-)/2 VOL; Output low, RL = 1k to (VS+ + VS-)/2 VOH; Output high, RL = 100k to (VS+ + VS-)/2 VOH; Output high, RL = 1k to (VS+ + VS-)/2
SR GBWP
Slew Rate Gain Bandwidth Product
2
FN7467.3 February 22, 2007
EL8188
Electrical Specifications
PARAMETER IS, ON VS+ = 5V, VS- = 0V, VCM = 0.1V, VO = 1.4V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C (Continued) TEST CONDITIONS MIN 35 30 IS, OFF Supply Current, Disabled 3 TYP 50 MAX 75 90 10 10 ISC+ Short Circuit Output Current RL = 10 to opposite supply 23 18 ISCShort Circuit Output Current RL = 10 to opposite supply 20 15 VS Minimum Supply Voltage 2.2 2.4 2.4 VINH VINL IENH Enable Pin High Level Enable Pin Low Level Enable Pin Input Current VEN = 5V 0.25 0.25 IENL Enable Pin Input Current VEN = 0V -0.5 -0.5 0 0.7 2 0.8 2 2.5 +0.5 +0.5 26 31 UNIT A A A A mA mA mA mA V V V V A A A A
DESCRIPTION Supply Current, Enabled
3
FN7467.3 February 22, 2007
EL8188 Typical Performance Curves
1 RL 10k VOUT = 0.2VP-P 0 GAIN (dB) GAIN (dB) VS = 1.25 -1 VS = 2.5V -2 VS = 1.0V -3 1k 10k 100k 1M
VS = 2.5V, TA = +25C, Unless Otherwise Specified
80 70 60 50 40 30 20 10 0 -10 -20 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) GAIN = 1 GAIN = 10 GAIN = 5 GAIN = 2 GAIN = 1k
RL 10k VOUT = 0.2VP-P GAIN = 500 GAIN = 200 GAIN = 100
FREQUENCY (Hz)
FIGURE 1. UNITY GAIN FREQUENCY RESPONSE at VARIOUS SUPPLY VOLTAGES
FIGURE 2. FREQUENCY RESPONSE at VARIOUS CLOSED LOOP GAINS
60 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) INPUT OFFSET VOLTAGE (V)
200 AV = -1 VCM = VDD/2 100
SUPPLY CURRENT A)
0
-100
-200 -0.5
0.5
1.5
2.5
3.5
4.5
5.5
OUTPUT VOLTAGE (V)
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 4. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE
INPUT BIAS, OFFSET CURRENT (fA)
250 INPUT OFFSET VOLTAGE (V)
20
150
10
IOS
50
IB0
-50
-150
-10
IB+
-250 -0.5
0.5
1.5
2.5
3.5
4.5
5.5
-20 -0.5
0.5
1.5
2.5
3.5
4.5
5.5
COMMON-MODE INPUT VOLTAGE (V)
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 5. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
FIGURE 6. INPUT BIAS, OFFSET CURRENT vs COMMONMODE INPUT VOLTAGE
4
FN7467.3 February 22, 2007
EL8188 Typical Performance Curves
100 80 60 GAIN (dB) PHASE 40 20 0 -20 10 GAIN 90 135 180 0 PHASE SHIFT () 45
(Continued) VS = 2.5V, TA = +25C, Unless Otherwise Specified (Continued)
100 90 80 70 GAIN (dB) 60 50 40 30 20 10 0 -10 10 100 1k 10k 100k 1M GAIN 180 PHASE 135 90 PHASE SHIFT ()
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. OPEN LOOP GAIN AND PHASE vs FREQUENCY (RL = 1k)
FIGURE 8. OPEN LOOP GAIN AND PHASE vs FREQUENCY (RL = 100k)
10 0 -10 -20 CMRR (dB) -30 -40 -50 -60 -70 -80 -90
VCM = 1VP-P RL = 100k AV = +1
10 0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -90
VS = 1VP-P RL = 100k AV = +1 -PSRR +PSRR
-100 10
100
1k
10k
100k
1M
-100 10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. CMRR vs FREQUENCY
FIGURE 10. PSRR vs FREQUENCY
1000
100 VOLTAGE NOISE (500nV/DIV)
VOLTAGE NOISE (nV/Hz)
100 VOLTAGE
10
10
1
CURRENT NOISE (pA/Hz)
2.8VP-P
CURRENT 1 1 10 100 1k 10k FREQUENCY (Hz) 0.1 100k
TIME (1s/DIV)
FIGURE 11. INPUT VOLTAGE AND CURRENT NOISE vs FREQUENCY
FIGURE 12. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
5
FN7467.3 February 22, 2007
EL8188 Typical Performance Curves
150 INPUT OFFSET VOLTAGE (V) 10 SAMPLES 100 50 0 -50 -100 -150 0
(Continued) VS = 2.5V, TA = +25C, Unless Otherwise Specified (Continued)
400 300 200 VOS (V) 100 0 -100 -200 -300 35 SOIC SAMPLES TYPICAL = 1.1V/C -40 -20 0 20 40 60 80 100 120
10
20
30
40
50
60
70
80
90
100
-400 -60
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 13. VOS vs TEMPERATURE
FIGURE 14. EL8188 SOIC VOS vs TEMPERATURE (VS = 5V)
800 600 400 VOS (V) 200 0 -200 -400 -600 -800 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 35 6 LD SOT-23 SAMPLES TYPICAL = 1.9V/C
FIGURE 15. EL8188 SOT VOS vs TEMPERATURE (VS = 5V)
20 15 VOS DRIFT (V) 10 5 0 -5 -10 -15 0
n = 10 MAX VOS DRIFT (V)
18 13 8 3 -2 -7 -12
n = 10 MAX
MEDIAN
MEDIAN
MIN 500 1000 HOURS 1500 1900
MIN 0 500 1000 HOURS 1500 1900
FIGURE 16. VOS DRIFT SOT-23 vs TIME
FIGURE 17. VOS DRIFT SOIC vs TIME
6
FN7467.3 February 22, 2007
EL8188 Pin Descriptions
SO PIN NUMBER 1 2 3 4 5 6 7 8 1 6 5 4 3 2 SOT-23 PIN NUMBER PIN NAME NC ININ+ VSNC OUT VS+ ENABLE Circuit 3 Circuit 4 Circuit 2 Circuit 1 Circuit 1 Circuit 4 EQUIVALENT CIRCUIT No internal connection Amplifier's inverting input Amplifier's non-inverting input Negative power supply No internal connection Amplifier's output Positive power supply Amplifier's enable pin with internal pull-down; Logic "1" selects the disabled state; Logic "0" selects the enabled state.
VS+ VS+
CAPACITIVELY COUPLED ESD CLAMP
DESCRIPTION
VS+ ININ+ VSENABLE
VS+ OUT
VS-
VSVSCIRCUIT 3 CIRCUIT 4
CIRCUIT 1
CIRCUIT 2
Application Information
Introduction
The EL8188 is a rail-to-rail input and output (RRIO), micropower, precision, single supply op amp with an enable feature. This amplifier is designed to operate from single supply (2.4V to 5.0V) or dual supply (1.2V to 2.5V) while drawing only 50A of supply current.The device achieves rail-to-rail input and output operation while eliminating the drawbacks of many conventional RRIO op amps.
Rail-to-Rail Output
A pair of complementary MOSFET devices achieves rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction, while the PMOS sources current to swing the output in the positive direction. The EL8188 with a 100k load swings to within 3mV of the supply rails.
Enable/Disable Feature
The EL8188 features an active low ENABLE pin that when pulled up to at least 2V disables the output, and drops the already low ICC to a 3A trickle. The ENABLE pin has an internal pull down, so an undriven pin pulls to the negative rail, thereby enabling the op amp by default. The high impedance output during disable allows for connecting multiple EL8188s together to implement a Mux Amp. The outputs are connected together and activating the appropriate ENABLE pin selects the desired channel. If utilizing non-unity gain op amp configurations, then the loading effects of the disabled amplifiers' feedback networks must be considered when evaluating the active amplifier's performance in Mux Amp configurations. Note that feedthrough from the IN+ to IN- pins occurs on any Mux Amp disabled channel where the input differential voltage exceeds 0.5V (e.g., active channel VOUT = 1V, while disabled channel VIN = GND), so the mux implementation is best suited for small signal applications. If large signals are required, use series IN+ resistors, or large value RFs, to keep the feedthrough current low enough to minimize the impact on the active channel. See the "Usage Implications" on page 8 for more details.
Rail-to-Rail Input
The PFET input stage of the EL8188 has an input commonmode voltage range that includes the negative and positive supplies without introducing offset errors or degrading performance like some existing rail-to-rail input op amps. Many rail-to-rail input stages use two differential input pairs: a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties result from using this topology. As the input signal moves from one supply rail to the other, the op amp switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in the input offset current's magnitude and polarity. The EL8188 achieves rail-to-rail input performance without sacrificing important precision specifications and without degrading distortion performance. The EL8188's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range.
7
FN7467.3 February 22, 2007
EL8188
IN+ and IN- Input Protection
In addition to ESD protection diodes to each supply rail, the EL8188 has additional back-to-back protection diodes across the differential input terminals (see "Circuit 1" on page 7). Obviously, one of these diodes conducts if the magnitude of the differential input voltage ever exceeds the diode's VF. Usage Implications If the input differential voltage is expected to exceed 0.5V, an external current limiting resistor must be used to ensure the input current never exceeds 5mA. For noninverting unity gain applications the current limiting can be via a series IN+ resistor, or via a feedback resistor of appropriate value. For other gain configurations, the series IN+ resistor is the best choice, unless the feedback (RF) and gain setting (RG) resistors are both sufficiently large to limit the input current to 5mA. Large differential input voltages can arise from several sources: 1) During open loop (comparator) operation. Used this way, the IN+ and IN- voltages don't track, so differentials arise. 2) When the amplifier is disabled but an input signal is still present. An RL or RG to GND keeps the IN- at GND, while the varying IN+ signal creates a differential voltage. Mux Amp applications are similar, except that the active channel VOUT determines the voltage on the IN- terminal. 3) When the slew rate of the input pulse is considerably faster than the op amp's slew rate. If the VOUT can't keep up with the IN+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. To avoid this issue, keep the input slew rate below 0.2V/s, or use appropriate current limiting resistors. Large (>2V) differential input voltages can also cause an increase in disabled ICC. the safe operating area. These parameters are related as follows:
T JMAX = T MAX + ( JA x PD MAX ) (EQ. 1)
where PDMAX is calculated using:
V OUTMAX PD MAX = V S x I SMAX + ( V S - V OUTMAX ) x --------------------------R
L
(EQ. 2)
where: * TMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation of the amplifier * VS = Supply voltage * IMAX = Maximum supply current of the amplifier * VOUTMAX = Maximum output voltage swing of the application * RL = Load resistance
Proper Layout Maximizes Precision
To achieve the optimum levels of high input impedance (i.e., low input currents) and low offset voltage, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a paramount concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 18 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents, mount components to the PC board using Teflon standoffs.
HIGH IMPEDANCE INPUT IN V+
ENABLE Input Protection
The ENABLE input has internal ESD protection diodes to both the positive and negative supply rails, limiting the input voltage range to within one diode beyond the supply rails (see "Circuit 2" on page 7). If the input voltage is expected to exceed VS+ or VS-, then an external series resistor should be added to limit the current to 5mA.
Output Current Limiting
The EL8188 has no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the "Absolute Maximum Rating" for "operating junction temperature", potentially resulting in the destruction of the device.
Power Dissipation
It is possible to exceed the +150C maximum junction temperature (TJMAX) under certain load and power-supply conditions. It is therefore important to calculate TJMAX for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in
FIGURE 18. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER
8
FN7467.3 February 22, 2007
EL8188
Typical Applications
VS+ + EL8188 VSR4 + 3V COAX R3 R2 K TYPE THERMOCOUPLE 10k 10k 100k VS+ + EL8188 VS-
GENERAL PURPOSE COMBINATION pH PROBE
410V/C + 5V
FIGURE 19. pH PROBE AMPLIFIER
A general-purpose combination pH probe has extremely high output impedance typically in the range of 10G to 12G. Low loss and expensive Teflon cables are often used to connect the pH probe to the meter electronics. Figure 19 details a low-cost alternative solution using the EL8188 and a low-cost coax cable. The EL8188 PMOS high impedance input senses the pH probe output signal and buffers it to drive the coax cable. Its rail-to-rail input nature also eliminates the need for a bias resistor network required by other amplifiers in the same application.
R1 100k
FIGURE 20. THERMOCOUPLE AMPLIFIER
Thermocouples are the most popular temperature sensing devices because of their low cost, interchangeability, and ability to measure a wide range of temperatures. In Figure 20, the EL8188 converts the differential thermocouple voltage into single-ended signal with 10X gain. The EL8188's rail-to-rail input characteristic allows the thermocouple to be biased at ground and permits the op amp to operate from a single 5V supply.
9
FN7467.3 February 22, 2007
EL8188 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
10
FN7467.3 February 22, 2007
EL8188 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES:
E1 2 3
E
A2 b c
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
D E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
(L1)
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 0 +3 -0
0.25
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN7467.3 February 22, 2007

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